Semiconductor memory device

ABSTRACT

A semiconductor memory device of an embodiment has stacked semiconductor memories, each semiconductor memory including first lines intersecting with second lines, and resistive change elements each disposed between one of the first lines and one of the second lines. In two of the semiconductor memories adjacent to each other in the stacking direction, either two of the first lines or two of the second lines are disposed along and in contact with each other. A first contact electrically connected to the second line of the uppermost semiconductor memory passes through a region between the second lines of each of the semiconductor memories located below the uppermost semiconductor memory, and a second contact electrically connected to the second line of each of the semiconductor memories located at an intermediate level passes through a region between the second lines of each of the semiconductor memories located below the intermediate level.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2019-166252, filed on Sep. 12, 2019, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to semiconductor memory devices.

BACKGROUND

Semiconductor memories including resistive change elements such as phase-change memory elements (hereinafter also referred to as “phase-change material (PCM) elements”) serving as storage elements disposed in intersections of wirings are known.

Such semiconductor memories may be stacked and integrated. In such a case, however, the chip size may be increased.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of a semiconductor memory device according to a first embodiment.

FIG. 2 is a cross-sectional view of the semiconductor memory device according to the first embodiment.

FIG. 3 is a cross-sectional view of a semiconductor memory device according to a second embodiment.

FIG. 4 is a cross-sectional view of a semiconductor memory device according to a third embodiment.

DETAILED DESCRIPTION

In a semiconductor memory including resistive change elements such as a phase-change memory elements (hereinafter also referred to as phase-change material (PCM) elements) serving as storage elements, a wiring (for example, a first bit line) intersects with another wiring (for example, a first word line) in a stacking manner, a second bit line is disposed to intersect with the first word line, a second word line is disposed to intersect with the second bit line, and each resistive change element is disposed at an intersection of a bit line and a word line. If wirings are further stacked, and a third bit line is disposed to intersect with the second word line and a third word line is disposed to intersect with the third bit line, a contact that electrically connects the third word line and a driving circuit for driving the third word line disposed on the lowest level of the semiconductor memory may contact the first word line or the second word line which is disposed below the third word line. This problem may be solved by dividing the word line that may possibly contact the contact. In such a case, however, another wiring that connects the divided word lines is needed, which increases the chip size. If the divided word lines are not connected by using another wiring, additional transistors may be needed to drive the divided word lines, which also increases the chip size.

A semiconductor memory capable of preventing an increase in chip size if having an increased number of layers will then be described by referring to embodiments below.

A semiconductor memory device according to an embodiment includes: a plurality of first wirings disposed at a first level and extending in a first direction; a second wiring and a third wiring disposed at a second level, a position of which in a second direction intersecting with the first direction is different from that of the first level, the second wiring and the third wiring extending in a third direction that intersects with the first direction and the second direction, and being separated from each other; a plurality of first resistive change elements each including a first terminal and a second terminal and disposed between one of the first wirings and one of the second wiring and the third wiring, the first terminal being electrically connected to the one of the first wirings, and the second terminal being electrically connected to the one of the second wiring and the third wiring; a fourth wiring disposed to be in contact with a face of the second wiring opposite to the first wirings and extending in the third direction; a fifth wiring disposed to be in contact with a face of the third wiring opposite to the first wirings, extending in the third direction, and separated from the fourth wiring; a plurality of sixth wirings disposed at a third level and extending in the first direction, the second level being between the first level and the third level; a plurality of second resistive change elements each including a third terminal and a fourth terminal and disposed between one of the fourth wiring and the fifth wiring and one of the sixth wirings, the third terminal being electrically connected to the one of the fourth wiring and the fifth wiring, and the fourth terminal being electrically connected to the one of the sixth wirings; a plurality of seventh wirings disposed to correspond to the sixth wirings and extending in the first direction, each of the seventh wirings being disposed to be in contact with a face of corresponding one of the sixth wirings opposite to the second resistive change elements; an eighth wiring and a ninth wiring disposed at a fourth level, extending in the third direction, and separated from each other, the third level being between the fourth level and the second level; a plurality of third resistive change elements each including a fifth terminal and a six terminal and disposed between one of the seventh wirings and one of the eighth wiring and the ninth wiring, the fifth terminal being electrically connected to the one of the seventh wirings, and the six terminal being electrically connected to the one of the eighth wiring and the ninth wiring; a tenth wiring disposed to be in contact with a face of the eighth wiring opposite to the seventh wirings and extending in the third direction; an eleventh wiring disposed to be in contact with a face of the ninth wiring opposite to the seventh wirings and extending in the third direction, and separated from the tenth wiring; a plurality of twelfth wirings disposed at a fifth level and extending in the first direction, the fourth level being between the fifth level and the third level; a plurality of fourth resistive change elements each including a seventh terminal and an eighth terminal and disposed between one of the tenth wiring and the eleventh wiring and one of the twelfth wirings, the seventh terminal being electrically connected to the one of the tenth wiring and the eleventh wiring, and the eighth terminal being electrically connected to the one of the twelfth wirings; a plurality of thirteenth wirings disposed to correspond to the twelfth wirings and extending in the first direction, each of the thirteenth wirings disposed to be in contact with a face of corresponding one of the twelfth wirings opposite to the fourth resistive change elements; a fourteenth wiring and a fifteenth wiring disposed at a sixth level, extending in the third direction, and separated from each other, the fifth level being between the sixth level and the fourth level, a region between the tenth wiring and the eleventh wiring, a region between the eighth wiring and the ninth wiring, a region between the fourth wiring and the fifth wiring, and a region between the second wiring and the third wiring being located at positions in the second direction from a portion of the fourteenth wiring; a plurality of fifth resistive change elements each including a ninth terminal and a tenth terminal and disposed between one of the thirteenth wirings and one of the fourteenth wiring and the fifteenth wiring, the ninth terminal being electrically connected to the one of the thirteenth wirings, and the tenth terminal being electrically connected to the one of the fourteenth wiring and the fifteenth wiring; a sixteenth wiring disposed to be in contact with a face of the fourteenth wiring opposite to the thirteenth wirings and extending in the third direction; a seventeenth wiring disposed to be in contact with a face of the fifteenth wiring opposite to the thirteenth wirings and extending in the third direction, and separated from the sixteenth wiring; a plurality of eighteenth wirings disposed at a seventh level and extending in the first direction, the sixth level being between the seventh level and the fifth level; a plurality of sixth resistive change elements each including an eleventh terminal and a twelfth terminal and disposed between one of the sixteenth wiring and the seventeenth wiring and one of the eighteenth wirings, the eleventh terminal being electrically connected to the one of the sixteenth wiring and the seventeenth wiring, and the twelfth terminal being electrically connected to the one of the eighteenth wirings; a first contact electrically connected to a portion of the third wiring; a second contact electrically connected to an end of the ninth wiring on a side of the eighth wiring, and passing through the region between the fourth wiring and the fifth wiring and the region between the second wiring and the third wiring; and a third contact electrically connected to the portion of the fourteenth wiring, and passing through the region between the tenth wiring and the eleventh wiring, the region between the eighth wiring and the ninth wiring, the region between the fourth wiring and the fifth wiring, and the region between the second wiring and the third wiring.

First Embodiment

A semiconductor memory device according to a first embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 is a cross-sectional view of the semiconductor memory device according to the first embodiment. The cross-sectional view shown in FIG. 1 shows a z-y plane. FIG. 2 shows a cross-sectional view taken along line J-J shown in FIG. 1.

The semiconductor memory device according to the first embodiment has a structure obtained by sequentially stacking a cross-point semiconductor memory 10 ₁, a cross-point semiconductor memory 10 ₂, a cross-point semiconductor memory 10 ₃, a cross-point semiconductor memory 10 ₄, a cross-point semiconductor memory 10 ₅, and a cross-point semiconductor memory 10 ₆. In the following descriptions, each memory cell of the respective semiconductor memories has a resistive change element serving as a storage element. The resistive change element is a PCM element in the following descriptions, but not limited thereto.

The semiconductor memory 10 ₁ includes a plurality of (nine in FIG. 1) bit lines BL₁₄ to BL₁₁₂, a plurality of (nine in FIG. 1) PCM elements 11 ₁₄ to 11 ₁₁₂, and a plurality of (two in FIG. 1) word lines WL₁₁ and WL₁₂. The bit lines BL₁₄ to BL₁₁₂, the PCM elements 11 ₁₄ to 11 ₁₁₂, and the word lines WL₁₁ and WL₁₂ are disposed at different levels in a z direction (the vertical direction in FIG. 1).

The bit lines BL₁₄ to BL₁₁₂ extend in a direction perpendicular to the plane of FIG. 1 (x direction). The word lines WL₁₁ and the word line WL₁₂ extend in a lateral direction in FIG. 1 (y direction), and separated from each other. In other words, there is a space between the word line WL₁₁ and the word line WL₁₂. One end of the PCM element 11 _(1j) is electrically connected to the bit line BL_(1j) (j=4, . . . , 12). The other end of each of the PCM elements 11 ₁₄ to 11 ₁₆ is electrically connected to the word line WL₁₁. The other end of each of the PCM elements 11 ₁₇ to 11 ₁₁₂ is electrically connected to the word line WL₁₂. The description “A and B are electrically connected” herein means that A and B may be directly connected or indirectly connected via a conductive member disposed between A and B.

The semiconductor memory 10 ₂ includes a plurality of (two in FIG. 1) word lines WL₂₁ and WL₂₂, a plurality of (nine in FIG. 1) bit lines BL₂₄ to BL₂₁₂, and a plurality of (nine in FIG. 1) PCM elements 11 ₂₄ to 11 ₂₁₂. The word lines WL₂₁ and WL₂₂, the PCM elements 11 ₂₄ to 11 ₂₁₂, and the bit lines BL₂₄ to BL₂₁₂ are disposed at different levels in the z direction (the vertical direction in FIG. 1).

The word line WL₂₁ and the word line WL₂₂ extend in the lateral direction in FIG. 1 (y direction), and separated from each other. The word line WL₂₁ and the word line WL₂₂ are disposed to be in electrical contact with the top faces of the word line WL₁₁ and the word line WL₁₂ of the semiconductor memory 10 ₁, respectively. The lengths of the word line WL₂₁ and the word line WL₂₂ in the y direction are substantially the same as the lengths of the word line WL₁₁ and the word line WL₁₂ in the y direction, respectively. The description “A and B are in electrical contact with each other” herein means that A and B may be electrically in direct contact with each other or in indirect contact with each other with a conductive member being disposed therebetween. There is a space between the word line WL₂₁ and the word line WL₂₂, like the word line WL₁₁ and the word line WL₁₂. The bit lines BL₂₄ to BL₂₁₂ extend in the direction perpendicular to the plane of FIG. 1 (x direction). One end of each of the PCM elements 11 ₂₄ to 11 ₂₆ is electrically connected to the word line WL₂₁. One end of each of the PCM elements 11 ₂₇ to 11 ₂₁₂ is electrically connected to the word line WL₂₂. The other end of the PCM element 11 _(2j) (j=4, . . . , 12) is electrically connected to the bit line BL_(2j).

The semiconductor memory 10 ₃ includes a plurality of (nine in FIG. 1) bit lines BL₃₄ to BL₃₁₂, a plurality of (nine in FIG. 1) PCM elements 11 ₃₄ to 11 ₃₁₂, and a plurality of (two in FIG. 1) word lines WL₃₁ and WL₃₂. The bit lines BL₃₄ to BL₃₁₂, the PCM elements 11 ₃₄ to 11 ₃₁₂, and the word line WL₃₁, WL₃₂ are disposed at different levels in the z direction (the vertical direction in FIG. 1).

The bit lines BL₃₄ to BL₃₁₂ extend in the direction perpendicular to the plane of FIG. 1 (x direction). The bit line BL_(3j) (j=4, . . . , 12) is arranged to be in electrical contact with the top face of the bit line BL₂₃ of the semiconductor memory 10 ₂. The word line WL₃₁ and the word line WL₃₂ extend in the lateral direction in FIG. 1 (y direction), and separated from each other. In other words, there is a space (region) between the word line WL₃₁ and the word line WL₃₂. The word line WL₃₁ is arranged at substantially the same location as the word line WL₁₁ and the word line WL₂₁ in the y direction. However, the length of the word line WL₃₁ in the y direction is longer than the length of each of the word line WL₁₁ and the word line WL₂₁ in the y direction to have a portion where a contact (not shown) is connected. The word line WL₃₂ is arranged at substantially the same location as the word line WL₁₂ and the word line WL₂₂ in the y direction. However, the length of the word line WL₃₂ in the y direction is longer than the length of each of the word line WL₁₂ and the word line WL₂₂ in the y direction to have a portion where a contact (not shown) is connected. For example, in FIG. 1, a contact VW₃₂ is disposed at a left end (on the word line WL₃₁ side) of the word line WL₃₂. The “end of a wiring” herein means a region of the wiring that is closer to an adjacent wiring in the wiring extending direction than any of resistive change elements connected to the wiring. Therefore, there are two ends for each wiring. The left end of the word line WL₃₂ means an end of the word line WL₃₂ on the side of the word line WL₃₁ that is arranged to the immediate left of the word line WL₃₂ in the y direction.

Therefore, the length in the y direction of the space between the word line WL₃₁ and the word line WL₃₂ is shorter than the length in the y direction of the space between the word line WL₁₁ and the word line WL₁₂. One end of the PCM element 11 _(3j) is electrically connected to the bit line BL_(3j) (j=4, . . . , 12). The other end of each of the PCM elements 11 ₃₄ to 11 ₃₆ is electrically connected to the word line WL₃₁. The other end of each of the PCM elements 11 ₃₇ to 11 ₃₁₂ is electrically connected to the word line WL₃₂.

The semiconductor memory 10 ₄ includes a plurality of (two in FIG. 1) word lines WL₄₁ and WL₄₂, a plurality of (nine in FIG. 1) bit lines BL₄₄ to BL₄₁₂, and a plurality of (nine in FIG. 1) PCM elements 11 ₄₄ to 11 ₄₁₂. The word lines WL₄₁ and WL₄₂, the PCM elements 11 ₄₄ to 11 ₄₁₂, and the bit lines BL₄₄ to BL₄₁₂ are disposed at different levels in the z direction (the vertical direction in FIG. 1).

The word line WL₄₁ and the word line WL₄₂ extend in the lateral direction in FIG. 1 (y direction), and separated from each other. The word line WL₄₁ and the word line WL₄₂ are disposed to be in electrical contact with the top faces of the word line WL₃₁ and the word line WL₃₂ of the semiconductor memory 10 ₃, respectively. The lengths of the word line WL₄₁ and the word line WL₄₂ in the y direction are substantially the same as the lengths of the word line WL₃₁ and the word line WL₃₂ in the y direction, respectively. Thus, like the word line WL₃₁ and the word line WL₃₂, there is a space between the word line WL₄₁ and the word line WL₄₂. The bit lines BL₄₄ to BL₄₁₂ extend in the direction perpendicular to the plane of FIG. 1 (x direction). One end of each of the PCM elements 11 ₄₄ to 11 ₄₆ is electrically connected to the word line WL₄₁. One end of each of the PCM elements 11 ₄₇ to 11 ₄₁₂ is electrically connected to the word line WL₄₂. The other end of the PCM element 11 _(4j) (j=4, . . . , 12) is electrically connected to the bit line BL_(4j).

The semiconductor memory 10 ₅ includes a plurality of (nine in FIG. 1) bit lines BL₅₄ to BL₅₁₂, a plurality of (nine in FIG. 1) PCM elements 11 ₅₄ to 11 ₅₁₂, and a plurality of (two in FIG. 1) word lines WL₅₁ and WL₅₂. The bit lines BL₅₄ to BL₅₁₂, the PCM elements 11 ₅₄ to 11 ₅₁₂, and the word lines WL₅₁ and WL₅₂ are disposed at different levels in the z direction (the vertical direction in FIG. 1).

The bit lines BL₅₄ to BL₅₁₂ extend in the direction perpendicular to the plane of FIG. 1 (x direction). The bit line BL_(5j) (j=4, . . . , 12) is arranged to be in electrical contact with the top face of the bit line BL_(4j) of the semiconductor memory 10 ₄. The word line WL₅₁ and the word line WL₅₂ extend in the lateral direction in FIG. 1 (y direction), and separated from each other. In other words, there is a space between the word line WL₅₁ and the word line WL₅₂. The word line WL₅₁ is arranged at a location that is different from the location of each of the word line WL₃₁ and the word line WL₄₁ in the y direction. The word line WL₅₂ is arranged at a location that is different from the location of each of the word line WL₃₂ and the word line WL₄₂ in the y direction. For example, in FIG. 1, the central portion in the y direction of the word line WL₅₁ is located above the central portion of the space between word line WL₁₁ and the word line WL₁₂ (in the z direction). One end of the PCM element 11 ₅₃ is electrically connected to the bit line BL_(5j) (j=4, . . . , 12). The other end of each of the PCM elements 11 ₅₄ to 11 ₅₆ is connected to the word line WL₅₁. The other end of each of the PCM elements 11 ₅₇ to 11 ₅₁₂ is electrically connected to the word line WL₅₂.

The semiconductor memory 10 ₆ includes a plurality of (two in FIG. 1) word lines WL₆₁ and WL₆₂, a plurality of (nine in FIG. 1) bit lines BL₆₄ to BL₆₁₂, and a plurality of (nine in FIG. 1) PCM elements 11 ₆₄ to 11 ₆₁₂. The word lines WL₆₁ and WL₆₂, the PCM elements 11 ₆₄ to 11 ₆₁₂, and the bit lines BL₆₄ to BL₆₁₂ are disposed at different levels in the z direction (the vertical direction in FIG. 1).

The word line WL₆₁ and the word line WL₆₂ extend in the lateral direction in FIG. 1 (y direction), and separated from each other. The word line WL₆₁ and the word line WL₆₂ are disposed to be in electrical contact with the top faces of the word line WL₅₁ and the word line WL₅₂ of the semiconductor memory 10 ₅, respectively. The lengths of the word line WL₆₁ and the word line WL₆₂ in the y direction are substantially the same as the lengths of the word line WL₅₁ and the word line WL₅₂ in the y direction, respectively. Thus, like the word line WL₅₁ and the word line WL₅₂, there is a space between the word line WL₆₁ and the word line WL₆₂. The bit lines BL₆₄ to BL₆₁₂ extend in the direction perpendicular to the plane of FIG. 1 (x direction). One end of each of the PCM elements 11 ₆₄ to 11 ₆₆ is electrically connected to the word line WL₆₁. One end of each of the PCM elements 11 ₆₇ to 11 ₆₁₂ is electrically connected to the word line WL₆₂. The other end of the PCM element 11 _(6j) (j=4, . . . , 12) is electrically connected to the bit line BL_(6j).

One end of each of three PCM elements that are not shown is electrically connected to each of the word lines WL₂₁, WL₃₁, and WL₄₁, and the other ends of the PCM elements are electrically connected to bit lines that are not shown. One end of each of three PCM elements that are not shown is electrically connected to each of the word lines WL₅₂ and WL₆₂, and the other ends of the PCM elements are electrically connected to bit lines that are not shown. Thus, in the semiconductor memory device shown in FIG. 1, one end of each of six PCM elements is electrically connected to each word line. The number of PCM elements electrically connected to each word line may be more than six.

The semiconductor memory device shown in FIG. 1 also includes driving circuits (for example, driving circuits 100 ₁₂, 100 ₃₂, 100 ₅₁, and 100 ₅₂) for driving the respective word lines, and a control circuit 200 for controlling the driving circuits. For example, the driving circuit 100 ₁₂ is connected to the word line WL₁₂ through a contact VW₁₂, the driving circuit 100 ₃₂ is connected to the word line WL₃₂ through a contact VW₃₂, the driving circuit 100 ₅₁ is connected to the word line WL₅₁ through a contact VW₅₁, and the driving circuit 100 ₅₂ is connected to the word line WL₅₂ through a contact VW₅₂. Since the word line WL₂₂ is arranged to be in contact with the top face of the word line WL₁₂, it is driven by the driving circuit 100 ₁₂. Since the word line WL₄₂ is arranged to be in contact with the top face of the word line WL₃₂, it is driven by the driving circuit 100 ₃₂. Since the word line WL₅₁ is arranged to be in contact with the top face of the word line WL₅₁, it is driven by the driving circuit 100 ₅₁. Since the word line WL₆₂ arranged to be in contact with the top face of the word line WL₅₂, it is driven by the driving circuit 100 ₅₂. The word lines WL₁₁ and WL₃₁ are driven by driving circuits, which are not shown, through contacts, which are not shown, either. The contact (not shown) for the word line WL₁₁ connects to a portion (for example a central portion) of the word line WL₁₁, like the contact for the word line WL₁₂. The contact (not shown) for the word line WL₃₁ connects to the left end of the word line WL₃₁, like the contact for the word line WL₃₂. Since the word lines WL₂₁ and WL₄₁ are in contact with the top faces of the word lines WL₁₁ and WL₃₁, respectively, they are also driven by the driving circuits that are not shown.

The contact VW₁₂ is formed to electrically connect to a portion (for example a central portion) of the word line WL₁₂. The contact VW₃₂ is formed to electrically connect to the left end (on the side of the word line WL₃₁) of the word line WL₃₂ and also to the driving circuit 100 ₃₂ through the space between the word line WL₁₁ and the word line WL₁₂. The bit line BL_(3j) connected to the PCM element 11 _(3j) (j=7, . . . , 12) that is further connected to the word line WL₃₂ is stacked on the bit line BL₂₃. As a result, the wiring resistance of this portion becomes lower than that of a single wiring. Therefore, the existence of the contact VW₃₂ at the end of the word line WL₃₂ does not affect the voltage drop caused by a write current or a read current.

The contact VW₅₁ is formed to electrically connect to a portion (for example a central portion) of the word line WL₅₁, and also to the driving circuit 100 ₅₁ through the space between the word line WL₃₁ and the word line WL₃₂ and the space between the word line WL₁₁ and the word line WL₁₂. The contact VW₅₂ is formed to electrically connect to a portion (for example a central portion) of the word line WL₅₂, and also to the driving circuit 100 ₅₂ through the space on the right side of the word lines WL₄₂ and WL₃₂ and the space on the right side of the word lines WL₂₂ and WL₁₂. The control circuit 200 also controls bit lines connected to PCM elements to be accessed.

Each driving circuit includes a p-channel transistor and an n-channel transistor connected in series. The gate of each of the series-connected p-channel transistor and n-channel transistor is connected to the control circuit 200. An intermediate node (connection node) of the series-connected transistors is electrically connected to the corresponding word line through the corresponding contact. Each of the driving circuits supplies a write current or a read current via the corresponding word line to the PCM element to be accessed.

Furthermore, in the semiconductor memory device according to the first embodiment, the bit line BL₁₄ is electrically connected to the bit line BL₄₄ through a contact VB₄₄, and to the control circuit 200 through a contact VB₁₄, as shown in FIG. 2. The bit line BL₃₄ is electrically connected to the bit line BL₆₄ through a contact VB₆₄, and the bit line BL₂₄ is electrically connected to the control circuit 200 through a contact VB₂₄.

The semiconductor memory device according to the first embodiment also includes stacked bit lines BL₂₄′ and BL₃₄′ located at a distance from the right end of the stacked bit lines BL₂₄ and BL₃₄ and extending in the x direction. The contact VB₄₄ is disposed to pass through the space between the bit lines BL₂₄, BL₃₄ and the bit lines BL₂₄′, BL₃₄′. Furthermore, a bit line BL₆₄′ extending in the x direction is disposed at a distance from the right end of the bit line BL₆₄. The bit line BL₆₄′ is electrically connected to the bit line BL₃₄′ through the contact VB₆₄′. The contact VB₆₄′ passes through the space on the right side of the bit lines BL₄₄, BL₅₄ and is electrically connected to the bit line BL₃₄′. The contact VB₆₄ passes through the space on the left side of the bit lines BL₄₄, BL₅₄ and electrically connected to the bit line BL₃₄. The contact VB₂₄ passes through the space on the left side of the bit line BL₁₄ and is electrically connected to the control circuit 200. The contact VB₂₄′ passes through the space on the right side of the bit line BL₁₄ and is electrically connected to the control circuit 200. The bit lines BL₄₄, BL₅₄ are located directly above the bit line BL₁₄, the bit line BL₆₄ is located directly above the bit lines BL₂₄, BL₃₄, and the bit line BL₆₄′ is located directly above the bit lines BL₂₄′, BL₃₄′. Therefore, the location of the bit line BL₁₄ is shifted along the x direction from the locations of the bit lines BL₂₄, BL₃₄, and BL₆₄, and also the locations of the bit lines BL₂₄′, BL₃₄′, and BL₆₄′. The location of the bit line BL₆₄ is shifted along the x direction from the location of the bit lines BL₄₄, BL₅₄, and the location of the bit line BL₆₄′ is shifted along the x direction from the location of the bit lines BL₄₄, BL₅₄.

As described above, in the first embodiment and second and third embodiments that will be described later, a bit line (for example, the bit line BL₁₄) of the first semiconductor memory 10 ₁ on the bottom and a bit line (for example, the bit line BL₄₄) of the fourth semiconductor memory 10 ₄, the location of which along the x direction is the same as the location of the bit line of the first semiconductor memory 10 ₁, are connected to each other through the contact VB₄₄, and a bit line (for example, the bit line BL₃₄) of the third semiconductor memory 10 ₃ and a bit line (for example, the bit line BL₆₄) of the sixth semiconductor memory 10 ₆, the location of which along the x direction is the same as the location of the bit line of the third semiconductor memory 10 ₃, are connected to each other through the contact VB₆₄. In other words, a bit line of the i^(th) (i=1, 2, 3, 4) semiconductor memory and a bit line of the (i+3)^(th) semiconductor memory, the location of which along the x direction is the same as the bit line of the i^(th) semiconductor memory, are electrically connected to each other through a contact.

Furthermore, in the semiconductor memory device according to the first embodiment, a plurality of (three in FIG. 2) sets of stacked word lines WL₁₁, WL₂₁ are disposed between the left region relative to the contact VB₄₄ of the bit line BL₁₄ and the right region relative to the contact VB₂₄ of the bit line BL₂₄. The PCM element 11 ₁₄ is disposed between the bit line BL₁₄ and each word line WL₁₁, and the PCM element 11 ₂₄ is disposed between the bit line BL₂₄ and each word line WL₂₁.

A plurality of (three in FIG. 2) sets of stacked word lines WL₁₁′, WL₂₁′ are disposed between the right region relative to the contact VB₄₄ of the bit line BL₁₄ and the left region relative to the contact VB₂₄′ of the bit line BL₂₄′. The PCM element 11 ₁₄′ is disposed between the bit line BL₁₄ and each word line and the PCM element 11 ₂₄′ is disposed between the bit line BL₂₄′ and each word line WL₂₁′.

A plurality of (three in FIG. 2) sets of stacked word lines WL₃₁, WL₄₁ are disposed between the left region relative to the contact VB₄₄ of the bit line BL₄₄ and the right region relative to the contact VB₆₄ of the bit line BL₃₄. The PCM element 11 ₃₄ is disposed between the bit line BL₃₄ and each word line WL₃₁, and the PCM element 11 ₄₄ is disposed between the bit line BL₄₄ and each word line WL₄₁.

A plurality of (three in FIG. 2) sets of stacked word lines WL₃₁′, WL₄₁′ are disposed between the right region relative to the contact VB₄₄ of the bit line BL₄₄ and the left region relative to the contact VB₆₄′ of the bit line BL₃₄′. The PCM element 11 ₃₄′ is disposed between the bit line BL₃₄ and each word line WL₃₁′ and the PCM element 11 ₄₄′ is disposed between the bit line BL₄₄′ and each word line WL₄₁′.

A plurality of (three in FIG. 2) sets of word lines WL₅₁, WL₆₁ are disposed between the right region relative to the contact VB₆₄ of the bit line BL₆₄ and the left region of the bit line BL₅₄. The PCM element 11 ₅₄ is disposed between the bit line BL₅₄ and each word line WL₅₁, and the PCM element 11 ₆₄ is disposed between the bit line BL₆₄ and each word line WL₆₁.

A plurality of (three in FIG. 2) sets of stacked word lines WL₅₁′, WL₆₁′ are disposed between the left region relative to the contact VB₆₄′ of the bit line BL₆₄′ and the right region of the bit line BL₅₄. The PCM element 11 ₅₄′ is disposed between the bit line BL₅₄ and each word line WL₅₁′, and the PCM element 11 ₆₄′ is disposed between the bit line BL₆₄′ and each word line WL₆₁′.

A plurality of sets of word lines and PCM elements connected to those word line sets, which are not shown, are disposed on the left region relative to the contact VB₂₄ of the bit line BL₂₄. A plurality of sets of word lines and PCM elements connected to those word line sets, which are not shown, are disposed on the left region relative to the contact VB₆₄ of the bit line BL₃₄. A plurality of sets of word lines and PCM elements connected to those word line sets, which are not shown, are disposed on the right region relative to the contact VB₂₄′ of the bit line BL₂₄′. A plurality of sets of word lines and PCM elements connected to those word line sets, which are not shown, are disposed on the right region relative to the contact VB₆₄′ of the bit line BL₃₄′. A plurality of sets of word lines and PCM elements connected to those word line sets, which are not shown, are disposed on the left region relative to the contact VB₆₄ of the bit line BL₆₄. A plurality of sets of word lines and PCM elements connected to those word line sets, which are not shown, are disposed on the right region relative to the contact VB₆₄′ of the bit line BL₆₄′.

In the first embodiment having the above-described structure and the second and third embodiments that will be described later, the PCM elements includes a phase-change material, the phase of which changes between crystal phase and amorphous phase. An example of the phase-change material is a chalcogenide alloy (for example, a GeSbTe alloy). The chalcogenide alloy contains a chalcogenide (GeSbTe). Other examples include a AsSbTe alloy, a TaSbTe alloy, a NbSbTe alloy, a VSbTe alloy, a NbSbSe alloy, a VSbSe alloy, a WSbTe alloy, a MoSbTe alloy, a CrSbTe alloy, a WSbSe alloy, a MoSbSe alloy, a CrSbSe alloy, and a SnSbTe alloy.

A phase-change material changes to the crystal phase having a low resistance value if it is heated, melted, and cooled slowly, and to the amorphous phase having a high resistance value if it is cooled rapidly. Therefore, if a PCM element is heated by applying a voltage between the corresponding word line and the corresponding bit line, and then the voltage is rapidly dropped, the phase-change material of the PCM element is cooled rapidly and changes to the amorphous phase that is in a high-resistance state. If the voltage is dropped slowly, the phase-change material of the PCM element is cooled slowly and changes to the crystal phase that is in a low-resistance state. Data (information) may be written to the PCM element in this manner. The data (information) may be read from the PCM element by applying a voltage between the corresponding word line and the corresponding bit line, and measuring a current caused to flow by the voltage application, thereby measuring the resistance of the PCM element, for example.

As described above, according to the first embodiment, the contact VW₅₁ is electrically connected to a driving circuit for the fifth semiconductor memory 10 ₅, for example the driving circuit 100 ₅₁, and the contact VW₃₂ is electrically connected to a driving circuit for the third semiconductor memory 10 ₃, for example the driving circuit 100 ₃₂, through the space between the word line WL₃₁ and the word line WL₃₂ of the third semiconductor memory 10 ₃, the space between the word line WL₂₁ and the word line WL₂₂ of the second semiconductor memory 10 ₂, and the space between the word line WL11 and the word line WL₁₂ of the first semiconductor memory 10 ₁.

Thus, a contact electrically connected to a word line (for example, the word line WL₆₁) included in the uppermost semiconductor memory 10 ₆ passes through the spaces between the word lines included in the semiconductor memories 10 ₄, 10 ₃, and 10 ₂ that are located at two or more levels below the uppermost semiconductor memory 10 ₆, and is electrically connected to the corresponding driving circuit. A contact electrically connected to one of the word lines included in any of the semiconductor memories 10 ₃, 10 ₄, 10 ₅, and 10 ₆ located at the third or higher level passes through the space between the word lines included in the semiconductor memory 10 ₁ disposed at the first level, or the space on the right or left side of either of the word lines included in the semiconductor memory 10 ₁ that is located substantially the same position as the word line electrically connected to the contact, and is electrically connected to the corresponding driving circuit. For example, the contact electrically connected to the word line WL₃₁ passes through the space at the left end of the word line WL₁₁ of the semiconductor memory 10 ₁ and electrically connected to the corresponding driving circuit.

As a result, a contact for the fifth semiconductor memory 10 ₅, for example the contact VW₅₁ electrically connecting a word line, for example the word line WL₅₁, and the driving circuit 100 ₅₁ that is located on the bottom does not contact the word lines of the first to fourth semiconductor memories 10 ₁ to 10 ₄. Therefore, it is not necessary to divide the word lines of the semiconductor memories located below the fifth semiconductor memory 10 ₅. As a result, an increase in chip size may be prevented.

Second Embodiment

FIG. 3 shows a semiconductor memory device according to a second embodiment. Like the semiconductor memory device according to the first embodiment, the semiconductor memory device according to the second embodiment has a structure in which a contact electrically connecting to a word line included in the uppermost semiconductor memory passes through the space between word lines included in semiconductor memories located two or more levels below the uppermost semiconductor memory to be electrically connected to a corresponding driving circuit. Furthermore, a contact electrically connecting to a word line of each of the semiconductor memories disposed at the third or higher levels passes through the space between the word lines of the semiconductor memory disposed at the first level, or the space on the right or left side of any of the word lines included in the semiconductor memory that is located at substantially the same position as the word line to which the contact is electrically connected, to be electrically connected to a corresponding driving circuit. The structure of the semiconductor memory device according to the second embodiment will be described below with reference to FIG. 3.

The semiconductor memory device according to the second embodiment has a structure obtained by sequentially stacking a cross-point semiconductor memory 10 ₁, a cross-point semiconductor memory 10 ₂, a cross-point semiconductor memory 10 ₃, a cross-point semiconductor memory 10 ₄, a cross-point semiconductor memory 10 ₅, a cross-point semiconductor memory 10 ₆, a cross-point semiconductor memory 10 ₇, and a cross-point semiconductor memory 10 ₈. In the following descriptions, each memory cell of the respective semiconductor memories has a resistive change element serving as a storage element. The resistive change element is a PCM element in the following descriptions, but not limited thereto.

The semiconductor memory 10 ₁ includes a plurality of (nine in FIG. 3) bit lines BL₁₄ to BL₁₁₂, a plurality of (nine in FIG. 3) PCM elements 11 ₁₄ to 11 ₁₁₂, and a plurality of (two in FIG. 3) word lines WL₁₁ and WL₁₂. The bit lines BL₁₄ to BL₁₁₂, the PCM elements 11 ₁₄ to 11 ₁₁₂, and the word lines WL₁₁ and WL₁₂ are disposed at different levels in a z direction (the vertical direction in FIG. 3).

The bit lines BL₁₄ to BL₁₁₂ extend in a direction perpendicular to the plane of FIG. 3 (x direction). The word line WL₁₁ and the word line WL₁₂ extend in a lateral direction in FIG. 3 (y direction), and separated from each other. In other words, there is a space between the word line WL₁₁ and the word line WL₁₂. One end of the PCM element 11 _(1j) is electrically connected to the bit line BL_(1j) (j=4, . . . , 12). The other end of each of the PCM elements 11 ₁₄ to 11 ₁₆ is electrically connected to the word line WL₁₁. The other end of each of the PCM elements 11 ₁₇ to 11 ₁₁₂ is electrically connected to the word line WL₁₂.

The semiconductor memory 10 ₂ includes a plurality of (two in FIG. 3) word lines WL₂₁ and WL₂₂, a plurality of (nine in FIG. 3) bit lines BL₂₄ to BL₂₁₂, and a plurality of (nine in FIG. 3) PCM elements 11 ₂₄ to 11 ₂₁₂. The word lines WL₂₁ and WL₂₂, the PCM elements 11 ₂₄ to 11 ₂₁₂, and the bit lines BL₂₄ to BL₂₁₂ are disposed at different levels in the z direction (the vertical direction in FIG. 3).

The word line WL₂₁ and the word line WL₂₂ extend in the lateral direction in FIG. 3 (y direction), and separated from each other. The word line WL₂₁ and the word line WL₂₂ are disposed to be in electrical contact with the top faces of the word line WL₁₁ and the word line WL₁₂ of the semiconductor memory 10 ₁, respectively. The lengths of the word line WL₂₁ and the word line WL₂₂ in the y direction are substantially the same as the lengths of the word line WL₁₁ and the word line WL₁₂ in the y direction, respectively. Thus, like the word line WL₁₁ and the word line WL₁₂, there is a space between the word line WL₂₁ and the word line WL₂₂. The bit lines BL₂₄ to BL₂₁₂ extend in the direction perpendicular to the plane of FIG. 3 (x direction). One end of each of the PCM elements 11 ₂₄ to 11 ₂₆ is electrically connected to the word line WL₂₁. One end of each of the PCM elements 11 ₂₇ to 11 ₂₁₂ is electrically connected to the word line WL₂₂. The other end of the PCM element 11 _(2j) (j=4, . . . , 12) is electrically connected to the bit line BL_(2j).

The semiconductor memory 10 ₃ includes a plurality of (nine in FIG. 3) bit lines BL₃₄ to BL₃₁₂, a plurality of (nine in FIG. 3) PCM elements 11 ₃₄ to 11 ₃₁₂, and a plurality of (two in FIG. 3) word lines WL₃₁ and WL₃₂. The bit lines BL₃₄ to BL₃₁₂, the PCM elements 11 ₃₄ to 11 ₃₁₂, and the word lines WL₃₁ and WL₃₂ are disposed at different levels in the z direction (the vertical direction in FIG. 3).

The bit lines BL₃₄ to BL₃₁₂ extend in the direction perpendicular to the plane of FIG. 3 (x direction). The bit line BL_(3j) (j=4, . . . , 12) is arranged to be in electrical contact with the top face of the bit line BL_(2j) of the semiconductor memory 10 ₂. The word line WL₃₁ and the word line WL₃₂ extend in the lateral direction in FIG. 3 (y direction), and separated from each other. In other words, there is a space between the word line WL₃₁ and the word line WL₃₂. The word line WL₃₁ is arranged at substantially the same location as the word line WL₁₁ and the word line WL₂₁ in the y direction. However, the length of the word line WL₃₁ in the y direction is longer than the length of each of the word line WL₁₁ and the word line WL₂₁ in the y direction to have a region where a contact (not shown) is disposed. The word line WL₃₂ is arranged at substantially the same location as the word line WL₁₂ and the word line WL₂₂ in the y direction. However, the length of the word line WL₃₂ in the y direction is longer than the length of each of the word line WL₁₂ and the word line WL₂₂ in the y direction to have a region where a contact VW₃₂ is disposed. For example, in FIG. 3, the contact VW₃₂ is disposed on a left and (on the word line WL₃₁ side) of the word line WL₃₂. Therefore, the length in the y direction of the space between the word line WL₃₁ and the word line WL₃₂ is shorter than the length in the y direction of the space between the word line WL₁₁ and the word line WL₁₂. One end of the PCM element 11 _(3j) is electrically connected to the bit line BL_(3j) (j=4, . . . , 12). The other end of each of the PCM elements 11 ₃₄ to 11 ₃₆ is electrically connected to the word line WL₃₁. The other end of each of the PCM elements 11 ₃₇ to 11 ₃₁₂ is electrically connected to the word line WL₃₂.

The semiconductor memory 10 ₄ includes a plurality of (two in FIG. 3) word lines WL₄₁ and WL₄₂, a plurality of (nine in FIG. 1) bit lines BL₄₄ to BL₄₁₂, and a plurality of (nine in FIG. 3) PCM elements 11 ₄₄ to 11 ₄₁₂. The word lines WL₄₁ and WL₄₂, the PCM elements 11 ₄₄ to 11 ₄₁₂, and the bit lines BL₄₄ to BL₄₁₂ are disposed at different levels in the z direction (the vertical direction in FIG. 3).

The word line WL₄₁ and the word line WL₄₂ extend in the lateral direction in FIG. 3 (y direction), and separated from each other. The word line WL₄₁ and the word line WL₄₂ are disposed to be in electrical contact with the top faces of the word line WL₃₁ and the word line WL₃₂ of the semiconductor memory 10 ₃, respectively. The lengths of the word line WL₄₁ and the word line WL₄₂ in the y direction are substantially the same as the lengths of the word line WL₃₁ and the word line WL₃₂ in the y direction, respectively. Thus, like the word line WL₃₁ and the word line WL₃₂, there is a space between the word line WL₄₁ and the word line WL₄₂. The bit lines BL₄₄ to BL₄₁₂ extend in the direction perpendicular to the plane of FIG. 3 (x direction). One end of each of the PCM elements 11 ₄₄ to 11 ₄₆ is electrically connected to the word line WL₄₁. One end of each of the PCM elements 11 ₄₇ to 11 ₄₁₂ is electrically connected to the word line WL₄₂. The other end of the PCM element 11 _(4j) (j=4, . . . , 12) is electrically connected to the bit line BL_(4j).

The semiconductor memory 10 ₅ includes a plurality of (nine in FIG. 3) bit lines BL₅₄ to BL₅₁₂, a plurality of (nine in FIG. 1) PCM elements 11 ₅₄ to 11 ₅₁₂, and a plurality of (two in FIG. 3) word lines WL₅₁ and WL₅₂. The bit lines BL₅₄ to BL₅₁₂, the PCM elements 11 ₅₄ to 11 ₅₁₂, and the word lines WL₅₁ and WL₅₂ are disposed at different levels in the z direction (the vertical direction in FIG. 3).

The bit lines BL₅₄ to BL₅₁₂ extend in the direction perpendicular to the plane of FIG. 3 (x direction). The bit line BL_(5j) (j=4, . . . , 12) is arranged to be in electrical contact with the top face of the bit line BL_(4j) of the semiconductor memory 10 ₄. The word line WL₅₁ and the word line WL₅₂ extend in the lateral direction in FIG. 3 (y direction), and separated from each other. In other words, there is a space between the word line WL₅₁ and the word line WL₅₂. The word line WL₅₁ is arranged at substantially the same location as the word line WL₁₁ and the word line WL₂₁ in the y direction. However, the length of the word line WL₅₁ in the y direction is longer than the length of each of the word line WL₁₁ and the word line WL₂₁ in the y direction to have a region where a contact VW₅₁ is disposed. The contact VW₅₁ is electrically connected to the word line WL₅₁ and also to the driving circuit 100 ₅₁. The word line WL₅₂ is arranged at substantially the same location as the word line WL₁₂ and the word line WL₂₂ in the y direction. However, the length of the word line WL₅₂ in the y direction is longer than the length of each of the word line WL₁₂ and the word line WL₂₂ in the y direction to have a region where a contact (not shown) is disposed. For example, in FIG. 3, the contact VW₅₁ connecting to the word line WL₅₁ is disposed at an end on the word line WL₅₂ side. Therefore, the length in the y direction of the space between the word line WL₅₁ and the word line WL₅₂ is shorter than the length in the y direction of the space between the word line WL₁₁ and the word line WL₁₂. In FIG. 3, the contact VW₅₂ connecting to the word line WL₅₂ is disposed at a right end of the word line WL₅₂.

One end of the PCM element 11 ₅₁ is electrically connected to the bit line BL_(5j) (j=4, . . . , 12). The other end of each of the PCM elements 11 ₅₄ to 11 ₅₆ is electrically connected to the word line WL₅₁. The other end of each of the PCM elements 11 ₅₇ to 11 ₅₁₂ is electrically connected to the word line WL₅₂.

The semiconductor memory 10 ₆ includes a plurality of (two in FIG. 3) word lines WL₆₁ and WL₆₂, a plurality of (nine in FIG. 1) bit lines BL₆₄ to BL₆₁₂, and a plurality of (nine in FIG. 1) PCM elements 11 ₆₄ to 11 ₆₁₂. The word lines WL₆₁ and WL₆₂, the PCM elements 11 ₆₄ to 11 ₆₁₂, and the bit lines BL₆₄ to BL₆₁₂ are disposed at different levels in the z direction (the vertical direction in FIG. 3).

The word line WL₆₁ and the word line WL₆₂ extend in the lateral direction in FIG. 3 (y direction), and separated from each other. The word line WL₆₁ and the word line WL₆₂ are disposed to be in electrical contact with the top faces of the word line WL₅₁ and the word line WL₅₂ of the semiconductor memory 10 ₅, respectively. The lengths of the word line WL₆₁ and the word line WL₆₂ in the y direction are substantially the same as the lengths of the word line WL₅₁ and the word line WL₅₂ in the y direction, respectively. Thus, like the word line WL₅₁ and the word line WL₅₂, there is a space between the word line WL₆₁ and the word line WL₆₂. The bit lines BL₆₄ to BL₆₁₂ extend in the direction perpendicular to the plane of FIG. 3 (x direction). One end of each of the PCM elements 11 ₆₄ to 11 ₆₆ is electrically connected to the word line WL₆₁. One end of each of the PCM elements 11 ₆₇ to 11 ₆₁₂ is electrically connected to the word line WL₆₂. The other end of the PCM element 11 _(6j) (j=4, . . . , 12) is electrically connected to the bit line BL_(6j).

The semiconductor memory 10 ₇ includes a plurality of (nine in FIG. 3) bit lines BL₇₄ to BL₇₁₂, a plurality of (nine in FIG. 1) PCM elements 11 ₇₄ to 11 ₇₁₂, a plurality of (two in FIG. 3) word lines WL₇₁ and WL₇₂. The bit lines BL₇₄ to BL₇₁₂, the PCM elements 11 ₇₄ to 11 ₇₁₂, and the word lines WL₇₁ and WL₇₂ are disposed at different levels in the z direction (the vertical direction in FIG. 3).

The bit lines BL₇₄ to BL₇₁₂ extend in the direction perpendicular to the plane of FIG. 3 (x direction). The bit line BL_(7j) (j=4, . . . , 12) is arranged to be in electrical contact with the top face of the bit line BL_(6j) of the semiconductor memory 10 ₆. The word line WL₇₁ and the word line WL₇₂ extend in the lateral direction in FIG. 3 (y direction), and separated from each other. In other words, there is a space between the word line WL₇₁ and the word line WL₇₂. The word line WL₇₁ is arranged at a location that is different from the locations of the word line WL₅₁ and the word line WL₆₁ in the y direction. The word line WL₇₂ is arranged at a location that is different from the locations of the word line WL₅₂ and the word line WL₆₂ in the y direction. For example, in FIG. 3, the central portion in the y direction of the word line WL₇₁ is located above the central portion of the space between the word line WL₁₁ and the word line WL₁₂ (in the z direction). One end of the PCM element 11 _(7j) is electrically connected to the bit line BL_(7j) (j=4, . . . , 12). The other end of each of the PCM elements 11 ₇₄ to 11 ₇₆ is electrically connected to the word line WL₇₁. The other end of each of the PCM elements 11 ₇₇ to 11 ₇₁₂ is electrically connected to the word line WL₇₂.

The semiconductor memory 10 ₈ includes a plurality of (two in FIG. 3) word lines WL₈₁ and WL₈₂, a plurality of (nine in FIG. 3) bit lines BL₈₄ to BL₈₁₂, and a plurality of (nine in FIG. 3) PCM elements 11 ₈₄ to 11 ₈₁₂. The word lines WL₈₁ and WL₈₂, the PCM elements 11 ₈₄ to 11 ₈₁₂, and the bit lines BL₈₄ to BL₈₁₂ disposed at different levels in the z direction (the vertical direction in FIG. 3).

The word line WL₈₁ and the word line WL₈₂ extend in a lateral direction in FIG. 3 (y direction), and separated from each other. The word line WL₈₁ and the word line WL₈₂ are disposed to be in electrical contact with the top faces of the word line WL₇₁ and the word line WL₇₂ of the semiconductor memory 10 ₇, respectively. The lengths of the word line WL₈₁ and the word line WL₈₂ in the y direction are substantially the same as the lengths of the word line WL₇₁ and the word line WL₇₂ in the y direction, respectively. Thus, like the word line WL₇₁ and the word line WL₇₂, there is a space between the word line WL₈₁ and the word line WL₈₂. The bit lines BL₈₄ to BL₈₁₂ extend in the direction perpendicular to the plane of FIG. 3 (x direction). One end of each of the PCM elements 11 ₈₄ to 11 ₈₆ is electrically connected to the word line WL₈₁. One end of each of the PCM elements 11 ₈₇ to 11 ₈₁₂ is electrically connected to the word line WL₈₂. The other end of the PCM element 11 _(8j) (j=4, . . . , 12) is electrically connected to the bit line BL_(8j).

One end of each of three PCM elements that are not shown is electrically connected to each of the word line WL₂₁, WL₃₁, WL₄₁, WL₅₁, and WL₆₁, and the other ends of the PCM elements are electrically connected to bit lines that are not shown. One end of each of three PCM elements that are not shown is electrically connected to each of the word lines WL₇₂ and WL₈₂, and the other ends of the PCM elements are electrically connected to bit lines that are not shown. Thus, in the semiconductor memory device shown in FIG. 3, one end of each of six PCM elements is electrically connected to each word line. The number of PCM elements electrically connected to each word line may be more than six.

The semiconductor memory device shown in FIG. 3 also includes driving circuits (for example, driving circuits 100 ₁₂, 100 ₃₂, 100 ₅₁, 100 ₅₂, 100 ₇₁, and 100 ₇₂) for driving the respective word lines, and a control circuit 200 for controlling the driving circuits. For example, the driving circuit 100 ₁₂ is connected to the word line WL₁₂ through a contact VW₁₂, the driving circuit 100 ₃₂ is connected to the word line WL₃₂ through a contact VW₃₂, the driving circuit 100 ₅₁ is connected to the word line WL₅₁ through a contact VW₅₁, and the driving circuit 100 ₅₂ is connected to the word line WL₅₂ through a contact VW₅₂. Since the word line WL₂₂ is arranged to be in contact with the top face of the word line WL₁₂, it is driven by the driving circuit 100 ₁₂. Since the word line WL₄₂ is arranged to be in contact with the top face of the word line WL₃₂, it is driven by the driving circuit 100 ₃₂. Since the word line WL₆₁ is arranged to be in contact with the top face of the word line WL₅₁, it is driven by the driving circuit 100 ₅₁. Since the word line WL₆₂ is arranged to be in contact with the top face of the word line WL₅₂, it is driven by the driving circuit 100 ₅₂. Since the word line WL₃₁ is arranged to be in contact with the top face of the word line WL₇₁, it is driven by the driving circuit 100 ₇₁. Since the word line WL₃₂ is arranged to be in contact with the top face of the word line WL₇₂, it is driven by the driving circuit 100 ₇₂.

The word lines WL₁₁ and WL₃₁ are driven by driving circuits, which are not shown, through contacts, which are not shown, either. As in the case of the contact of the word line WL₁₂, the contact for the word line WL₁₁ is formed to electrically connect to a portion (for example a central portion) of the word line WL₁₁. As in the case of the contact of the word line WL₃₂, the contact for the word line WL₃₁ is formed to electrically connect to a portion (for example a left end) of the word line WL₃₁. Since the word lines WL₂₁ and WL₄₁ are in contact with the top faces of the word lines WL₁₁ and WL₃₁, respectively, they are driven by the aforementioned driving circuits that are not shown.

The contact VW₁₂ is formed to electrically connect to a portion (for example a central portion) of the word line WL₁₂. The contact VW₃₂ is formed to electrically connect to an end of the word line WL₃₂ on the word line WL₃₁ side, and also to the driving circuit 100 ₃₂ via a space between the word line WL₁₁ and the word line WL₁₂. The bit line BL_(3j) for the PCM element 11 _(3j) (j=7 . . . , 12) connecting to the word line WL₃₂ is stacked on the bit line BL_(2j). As a result, the wiring resistance of this portion is lower than that of a single wiring. Therefore, the existence of the contact VW₃₂ at the end of the word line WL₃₂ does not affect the voltage drop caused by a write current or a read current.

The contact VW₅₁ is formed to electrically connect to an end (right end) of the word line WL₅₁ on the word line WL₅₂ side and also to the driving circuit 100 ₅₁ through the space between the word line WL₃₁ and the word line WL₃₂ and the space between the word line WL₁₁ and the word line WL₁₂. The contact VW₅₂ is formed to electrically connect to a right end of the word line WL₅₂ and also to the driving circuit 100 ₅₂ through the space on the right side of the word lines WL₄₂ and WL₃₂ and the space on the right side of the word lines WL₂₂ and WL₁₂. The contact VW₇₁ is formed to electrically connect to a portion (for example a central portion) of the word line WL₇₁, and also to the driving circuit 100 ₇₁ through the space between the word line WL₅₁ and the word line WL₅₂, the space between the word line WL₃₁ and the word line WL₃₂, and the space between the word line WL₁₁ and the word line WL₁₂. The contact VW₇₂ is formed to electrically connect to a portion (for example a central portion) of the word line WL₇₁ and also to the driving circuit 100 ₇₂ through the space on the right side of the word line WL₅₂, the space on the right side of the word line WL₃₂, and the space on the right side of the word line WL₁₂. The control circuit 200 also controls bit lines connected to PCM elements to be accessed.

As in the first embodiment, each driving circuit includes a p-channel transistor and an n-channel transistor connected in series. The gate of each of the series-connected p-channel transistor and n-channel transistor is connected to the control circuit 200. An intermediate node (connection node) of the series-connected transistors is electrically connected to a central portion of the corresponding word line. Each of the driving circuits supplies a write current or a read current via the corresponding word line to the PCM element to be accessed. Each of the PCM elements has the same structure as that of the first embodiment.

As described above, the semiconductor memory device according to the second embodiment has a structure in which the contact VW₇₁ electrically connected to the word line included in the uppermost semiconductor memory 10 ₈ is also electrically connected to the corresponding driving circuit 100 ₇₁ through the space between adjacent word lines of each of the semiconductor memories 10 ₆, 10 ₅, 10 ₄, 10 ₃, 10 ₂, and 10 ₁, which are arranged two or more levels below the uppermost semiconductor memory. Each of the contacts electrically connected to one of the word lines included in any of the semiconductor memories 10 ₆, 10 ₅, 10 ₄, and 10 ₃ arranged at the third or higher level is electrically connected to the corresponding driving circuit through the space between the word lines included in the semiconductor memory 10 ₁ disposed at the first level, or the space on the right or left side of the corresponding word line included in the semiconductor memory 10 ₁ arranged on the first layer, which is disposed at substantially the same position as the word line to which the contact is electrically connected.

Thus, the contact VW₇₁, for example, for connecting one of the word lines included in the eighth semiconductor memory 10 ₈, for example the word line WL₈₁, and the driving circuit 100 ₇₁ located at the lowermost level, does not contact the word lines included in the first to sixth semiconductor memories 10 ₁ to 10 ₆. Therefore, it is not necessary to divide the word lines of the semiconductor memories located below the eighth semiconductor memory 10 ₈. As a result, an increase in chip size may be prevented.

Third Embodiment

FIG. 4 shows a semiconductor memory device according to a third embodiment. The semiconductor memory device according to the third embodiment has a structure obtained by sequentially stacking a cross-point semiconductor memory 10 ₁, a cross-point semiconductor memory 10 ₂, a cross-point semiconductor memory 10 ₃, and a cross-point semiconductor memory 10 ₄. In the following descriptions, each memory cell of the respective semiconductor memories has a resistive change element serving as a storage element. The resistive change element is a PCM element in the following descriptions, but not limited thereto.

The semiconductor memory 10 ₁ includes a plurality of (nine in FIG. 4) bit lines BL₁₄ to BL₁₁₂, a plurality of (nine in FIG. 4) PCM elements 11 ₁₄ to 11 ₁₁₂, a plurality of (two in FIG. 4) word lines WL₁₁ and WL₁₂. The bit lines BL₁₄ to BL₁₁₂, the PCM elements 11 ₁₄ to 11 ₁₁₂, and the word lines WL₁₁ and WL₁₂ are disposed at different levels in a z direction (the vertical direction in FIG. 4).

The bit lines BL₁₄ to BL₁₁₂ extend in a direction perpendicular to the plane of FIG. 4 (x direction). The word line WL₁₁ and the word line WL₁₂ extend in a lateral direction in FIG. 4 (y direction), and separated from each other. In other words, there is a space between the word line WL₁₁ and the word line WL₁₂. One end of the PCM element 11 _(1j) is electrically connected to the bit line BL_(1j) (j=4, . . . , 12). The other end of each of the PCM elements 11 ₁₄ to 11 ₁₆ is electrically connected to the word line WL₁₁. The other end of each of the PCM elements 11 ₁₇ to 11 ₁₁₂ is electrically connected to the word line WL₁₂.

The semiconductor memory 10 ₂ includes a plurality of (two in FIG. 4) word lines WL₂₁ and WL₂₂, a plurality of (nine in FIG. 4) bit lines BL₂₄ to BL₂₁₂, and a plurality of (nine in FIG. 4) PCM elements 11 ₂₄ to 11 ₂₁₂. The word lines WL₂₁ and WL₂₂, the PCM elements 11 ₂₄ to 11 ₂₁₂, and the bit lines BL₂₄ to BL₂₁₂ are disposed at different levels in the z direction (the vertical direction in FIG. 4).

The word line WL₂₁ and the word line WL₂₂ extend in the lateral direction in FIG. 4 (y direction), and separated from each other. The word line WL₂₁ and the word line WL₂₂ are disposed to be in electrical contact with the top faces of the word line WL₁₁ and the word line WL₁₂ of the semiconductor memory 10 ₁, respectively. The lengths of the word line WL₂₁ and the word line WL₂₂ in the y direction are substantially the same as the lengths of the word line WL₁₁ and the word line WL₁₂ in the y direction, respectively. Thus, like the word line WL₁₁ and the word line WL₁₂, there is a space between the word line WL₂₁ and the word line WL₂₂. The bit lines BL₂₄ to BL₂₁₂ extend in the direction perpendicular to the plane of FIG. 4 (x direction). One end of each of the PCM elements 11 ₂₄ to 11 ₂₆ is electrically connected to the word line WL₂₁. One end of each of the PCM elements 11 ₂₇ to 11 ₂₁₂ is electrically connected to the word line WL₂₂. The other end of the PCM element 11 _(2j) (j=4, . . . , 12) is electrically connected to the bit line BL_(2j).

The semiconductor memory 10 ₃ includes a plurality of (nine in FIG. 4) bit lines BL₃₄ to BL₃₁₂, a plurality of (nine in FIG. 4) PCM elements 11 ₃₄ to 11 ₃₁₂, and a plurality of (two in FIG. 4) word lines WL₃₁ and WL₃₂. The bit lines BL₃₄ to BL₃₁₂, the PCM elements 11 ₃₄ to 11 ₃₁₂, and the word lines WL₃₁ and WL₃₂ are disposed at different levels in the z direction (the vertical direction in FIG. 4).

The bit lines BL₃₄ to BL₃₁₂ extend in the direction perpendicular to the plane of FIG. 4 (x direction). The bit line BL_(3j) (j=4, . . . , 12) is arranged to be in electrical contact with the top face of the bit line BL_(2j) of the semiconductor memory 10 ₂. The word line WL₃₁ and the word line WL₃₂ extend in the lateral direction in FIG. 4 (y direction), and separated from each other. In other words, there is a space between the word line WL₃₁ and the word line WL₃₂.

The word line WL₃₁ is arranged at a different location from the word line WL₁₁ and the word line WL₂₁ in the y direction, and the word line WL₃₂ is arranged at a different location from the word line WL₁₂ and the word line WL₂₂. For example, in FIG. 4, a central portion in the y direction of the word line WL₃₁ is located above (z direction) a central portion of the space between the word line WL₁₁ and the word line WL₁₂. One end of the PCM element 11 _(3j) is electrically connected to the bit line BL_(3j) (j=4, . . . , 12). The other end of each of the PCM elements 11 ₃₄ to 11 ₃₆ is electrically connected to the word line WL₃₁. The other end of each of the PCM elements 11 ₃₇ to 11 ₃₁₂ is electrically connected to the word line WL₃₂.

The semiconductor memory 10 ₄ includes a plurality of (two in FIG. 4) word lines WL₄₁ and WL₄₂, a plurality of (nine in FIG. 4) bit lines BL₄₄ to BL₄₁₂, and a plurality of (nine in FIG. 4) PCM elements 11 ₄₄ to 11 ₄₁₂. The word lines WL₄₁ and WL₄₂, the PCM elements 11 ₄₄ to 11 ₄₁₂, and the bit lines BL₄₄ to BL₄₁₂ are disposed at different levels in the z direction (the vertical direction in FIG. 4).

The word line WL₄₁ and the word line WL₄₂ extend in the lateral direction in FIG. 4 (y direction), and separated from each other. The word line WL₄₁ and the word line WL₄₂ are disposed to be in electrical contact with the top faces of the word line WL₃₁ and the word line WL₃₂ of the semiconductor memory 10 ₃, respectively. The lengths of the word line WL₄₁ and the word line WL₄₂ in the y direction are substantially the same as the lengths of the word line WL₃₁ and the word line WL₃₂ in the y direction, respectively. Thus, like the word line WL₃₁ and the word line WL₃₂, there is a space between the word line WL₄₁ and the word line WL₄₂. The bit lines BL₄₄ to BL₄₁₂ extend in the direction perpendicular to the plane of FIG. 4 (x direction). One end of each of the PCM elements 11 ₄₄ to 11 ₄₆ is electrically connected to the word line WL₄₁. One end of each of the PCM elements 11 ₄₇ to 11 ₄₁₂ is electrically connected to the word line WL₄₂. The other end of the PCM element 11 _(4j) (j=4, . . . , 12) is electrically connected to the bit line BL_(4j).

One end of each of three PCM elements that are not shown is electrically connected to each of the word lines WL₁₁ and WL₂₁, and the other ends of the PCM elements are electrically connected to bit lines that are not shown. One end of each of three PCM elements that are not shown is electrically connected to each of the word lines WL₃₂ and WL₄₂, and the other ends of the PCM elements are electrically connected to bit lines that are not shown. Thus, in the semiconductor memory device shown in FIG. 4, one end of each of six PCM elements is electrically connected to each word line. The number of PCM elements electrically connected to each word line may be more than six.

The semiconductor memory device according to the third embodiment shown in FIG. 4 also includes driving circuits (for example, driving circuits 100 ₁₂, 100 ₃₁, 100 ₃₂) for driving the respective word lines, and a control circuit 200 for controlling the driving circuits. For example, the driving circuit 100 ₁₂ is connected to the word line WL₁₂ through a contact VW₁₂, the driving circuit 100 ₃₁ is connected to the word line WL₃₁ through a contact VW₃₁, and the driving circuit 100 ₃₂ is connected to the word line WL₃₂ through a contact VW₃₂. Since the word line WL₂₂ is arranged to be in contact with the top face of the word line WL₁₂, it is driven by the driving circuit 100 ₁₂. Since the word line WL₄₁ is arranged to be in contact with the top face of the word line WL₃₁, it is driven by the driving circuit 100 ₃₁. Since the word line WL₄₂ is arranged to be in contact with the top face of the word line WL₃₂, it is driven by the driving circuit 100 ₃₂. The word line WL₁₁ is driven by a driving circuit, which is not shown, through a contact that is not shown, either. As in the case of the contact of the word line WL₁₂, the contact for the word line WL₁₁ is formed to electrically connect to a portion (for example a central portion) of the word line WL₁₁. Since the word line WL₂₁ is arranged to be in contact with the top face of the word line WL₁₁, the word line WL₂₁ is driven by the driving circuit that is not shown.

The contact VW₁₂ is formed to electrically connect to a portion (for example a central portion) of the word line WL₁₂. The contact VW₃₁ is formed to electrically connect to a portion (for example a central portion) of the word line WL₃₁, and also to the driving circuit 100 ₃₁ through the space between the word line WL₁₁ and the word line WL₁₂. The contact VW₃₂ is formed to electrically connect to a portion (for example a central portion) of the word line WL₃₂, and also to the driving circuit 100 ₃₂ through a space on the right side of the word line WL₂₂. The control circuit 200 also controls bit lines connected to PCM elements to be accessed.

Each driving circuit includes a p-channel transistor and an n-channel transistor connected in series. The gate of each of the series-connected p-channel transistor and n-channel transistor is connected to the control circuit 200. An intermediate node (connection node) of the series-connected transistors is electrically connected to a central portion of the corresponding word line. Each of the driving circuits supplies a write current or a read current via the corresponding word line to the PCM element to be accessed.

According to the third embodiment, the contact VW₃₁ for example, is electrically connected to the driving circuit for the fourth semiconductor memory 10 ₄, for example the driving circuit 100 ₃₁, through a space between the word line WL₂₁ and the word line WL₂₂ of the second semiconductor memory 10 ₂, and a space between the word line WL₁₁ and the word line WL₁₂ of the first semiconductor memory 10 ₁. Furthermore, the contact VW₃₂ is electrically connected to the driving circuit 100 ₃₂ through a space on the right side of the word line WL₂₂ of the second semiconductor memory 10 ₂ and a space on the right side of the word line WL₁₂ of the first semiconductor memory 10 ₁.

Thus, the contact VW₃₁ electrically connected to the word line included in the uppermost semiconductor memory 10 ₄ (for example, the word line WL₄₁) is also electrically connected to the corresponding driving circuit 100 ₃₁ through the space between adjacent word lines of each of the semiconductor memories 10 ₂ and 10 ₁ arranged two or more levels below the uppermost semiconductor memory. The contact VW₃₂ electrically connected to the word line WL₄₂ is electrically connected to the driving circuit 100 ₃₂ through a space on the right side of the word line WL₂₂ included in the second semiconductor memory 10 ₂ and the word line WL₁₂ included in the first semiconductor memory 10 ₁.

Thus, the contact VW₃₁, for example, for connecting one of the word lines included in the fourth semiconductor memory 10 ₄, for example the word line WL₄₁, and the driving circuit 100 ₃₁ located at the lowermost level, does not contact the word lines included in the first and the second semiconductor memories 10 ₁ and 10 ₂. Therefore, it is not necessary to divide the word lines of the semiconductor memories located below the fourth semiconductor memory 10 ₄. As a result, an increase in chip size may be prevented.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions. 

The invention claimed is:
 1. A semiconductor memory device comprising: a plurality of first wirings disposed at a first level and extending in a first direction; a second wiring and a third wiring disposed at a second level, a position of which in a second direction intersecting with the first direction is different from that of the first level, the second wiring and the third wiring extending in a third direction that intersects with the first direction and the second direction, and being separated from each other; a plurality of first resistive change elements each including a first terminal and a second terminal and disposed between one of the first wirings and one of the second wiring and the third wiring, the first terminal being electrically connected to the one of the first wirings, and the second terminal being electrically connected to the one of the second wiring and the third wiring; a fourth wiring disposed to be in contact with a face of the second wiring opposite to the first wirings and extending in the third direction; a fifth wiring disposed to be in contact with a face of the third wiring opposite to the first wirings, extending in the third direction, and separated from the fourth wiring; a plurality of sixth wirings disposed at a third level and extending in the first direction, the second level being between the first level and the third level; a plurality of second resistive change elements each including a third terminal and a fourth terminal and disposed between one of the fourth wiring and the fifth wiring and one of the sixth wirings, the third terminal being electrically connected to the one of the fourth wiring and the fifth wiring, and the fourth terminal being electrically connected to the one of the sixth wirings; a plurality of seventh wirings disposed to correspond to the sixth wirings and extending in the first direction, each of the seventh wirings being disposed to be in contact with a face of corresponding one of the sixth wirings opposite to the second resistive change elements; an eighth wiring and a ninth wiring disposed at a fourth level, extending in the third direction, and separated from each other, the third level being between the fourth level and the second level; a plurality of third resistive change elements each including a fifth terminal and a six terminal and disposed between one of the seventh wirings and one of the eighth wiring and the ninth wiring, the fifth terminal being electrically connected to the one of the seventh wirings, and the six terminal being electrically connected to the one of the eighth wiring and the ninth wiring; a tenth wiring disposed to be in contact with a face of the eighth wiring opposite to the seventh wirings and extending in the third direction; an eleventh wiring disposed to be in contact with a face of the ninth wiring opposite to the seventh wirings and extending in the third direction, and separated from the tenth wiring; a plurality of twelfth wirings disposed at a fifth level and extending in the first direction, the fourth level being between the fifth level and the third level; a plurality of fourth resistive change elements each including a seventh terminal and an eighth terminal and disposed between one of the tenth wiring and the eleventh wiring and one of the twelfth wirings, the seventh terminal being electrically connected to the one of the tenth wiring and the eleventh wiring, and the eighth terminal being electrically connected to the one of the twelfth wirings; a plurality of thirteenth wirings disposed to correspond to the twelfth wirings and extending in the first direction, each of the thirteenth wirings disposed to be in contact with a face of corresponding one of the twelfth wirings opposite to the fourth resistive change elements; a fourteenth wiring and a fifteenth wiring disposed at a sixth level, extending in the third direction, and separated from each other, the fifth level being between the sixth level and the fourth level, a region between the tenth wiring and the eleventh wiring, a region between the eighth wiring and the ninth wiring, a region between the fourth wiring and the fifth wiring, and a region between the second wiring and the third wiring being located at positions in the second direction from a portion of the fourteenth wiring; a plurality of fifth resistive change elements each including a ninth terminal and a tenth terminal and disposed between one of the thirteenth wirings and one of the fourteenth wiring and the fifteenth wiring, the ninth terminal being electrically connected to the one of the thirteenth wirings, and the tenth terminal being electrically connected to the one of the fourteenth wiring and the fifteenth wiring; a sixteenth wiring disposed to be in contact with a face of the fourteenth wiring opposite to the thirteenth wirings and extending in the third direction; a seventeenth wiring disposed to be in contact with a face of the fifteenth wiring opposite to the thirteenth wirings and extending in the third direction, and separated from the sixteenth wiring; a plurality of eighteenth wirings disposed at a seventh level and extending in the first direction, the sixth level being between the seventh level and the fifth level; a plurality of sixth resistive change elements each including an eleventh terminal and a twelfth terminal and disposed between one of the sixteenth wiring and the seventeenth wiring and one of the eighteenth wirings, the eleventh terminal being electrically connected to the one of the sixteenth wiring and the seventeenth wiring, and the twelfth terminal being electrically connected to the one of the eighteenth wirings; a first contact electrically connected to a portion of the third wiring; a second contact electrically connected to an end of the ninth wiring on a side of the eighth wiring, and passing through the region between the fourth wiring and the fifth wiring and the region between the second wiring and the third wiring; and a third contact electrically connected to the portion of the fourteenth wiring, and passing through the region between the tenth wiring and the eleventh wiring, the region between the eighth wiring and the ninth wiring, the region between the fourth wiring and the fifth wiring, and the region between the second wiring and the third wiring.
 2. The semiconductor memory device according to claim 1, further comprising: a first driving circuit configured to drive the third wiring through the first contact; a second driving circuit configured to drive the ninth wiring through the second contact; and a third driving circuit configured to drive the fourteenth wiring through the third contact.
 3. The semiconductor memory device according to claim 1, wherein at least one of the first to the sixth resistive change elements contain chalcogenide.
 4. The semiconductor memory device according to claim 1, wherein a length of the ninth wiring in the third direction is longer than a length of each of the third wiring and the fifth wiring in the third direction.
 5. The semiconductor memory device according to claim 1, wherein one of the first wirings corresponds to one of the sixth wirings, one of the twelfth wirings, and one of the eighteenth wirings in the second direction, wherein one of the seventh wirings corresponds to one of the eighteenth wirings in the second direction, wherein a position of the one of the first wirings is different from a position of corresponding one of the sixth wirings in the first direction and a position of corresponding one of the eighteenth wirings in the first direction, wherein the position of the one of the first wirings is the same as a position of corresponding one of the twelfth wirings in the first direction, and wherein a position of the one of the seventh wirings is the same as a position of corresponding one of the eighteenth wirings in the first direction, and the one of the first wirings is electrically connected to corresponding one of the twelfth wirings through a fourth contact, and the one of the seventh wirings is electrically connected to corresponding one of the eighteenth wirings through a fifth contact.
 6. A semiconductor memory device comprising: a plurality of first wirings disposed at a first level and extending in a first direction; a second wiring and a third wiring disposed at a second level, a position of which in a second direction intersecting with the first direction is different from that of the first level, the second wiring and the third wiring extending in a third direction that intersects with the first direction and the second direction, and being separated from each other; a plurality of first resistive change elements each including a first terminal and a second terminal and disposed between one of the first wirings and one of the second wiring and the third wiring, the first terminal being electrically connected to the one of the first wirings, and the second terminal being electrically connected to the one of the second wiring and the third wiring; a fourth wiring disposed to be in contact with a face of the second wiring opposite to the first wirings and extending in the third direction; a fifth wiring disposed to be in contact with a face of the third wiring opposite to the first wirings, extending in the third direction, and separated from the fourth wiring; a plurality of sixth wirings disposed at a third level and extending in the first direction, the second level being between the first level and the third level; a plurality of second resistive change elements each including a third terminal and a fourth terminal and disposed between one of the fourth wiring and the fifth wiring and one of the sixth wirings, the third terminal being electrically connected to the one of the fourth wiring and the fifth wiring, and the fourth terminal being electrically connected to the one of the sixth wirings; a plurality of seventh wirings disposed to correspond to the sixth wirings and extending in the first direction, each of the seventh wirings being disposed to be in contact with a face of corresponding one of the sixth wirings opposite to the second resistive change elements; an eighth wiring and a ninth wiring disposed at a fourth level, extending in the third direction, and separated from each other, the third level being between the fourth level and the second level; a plurality of third resistive change elements each including a fifth terminal and a six terminal and disposed between one of the seventh wirings and one of the eighth wiring and the ninth wiring, the fifth terminal being electrically connected to the one of the seventh wirings, and the six terminal being electrically connected to the one of the eighth wiring and the ninth wiring; a tenth wiring disposed to be in contact with a face of the eighth wiring opposite to the seventh wirings and extending in the third direction; an eleventh wiring disposed to be in contact with a face of the ninth wiring opposite to the seventh wirings and extending in the third direction, and separated from the tenth wiring; a plurality of twelfth wirings disposed at a fifth level and extending in the first direction, the fourth level being between the fifth level and the third level; a plurality of fourth resistive change elements each including a seventh terminal and an eighth terminal and disposed between one of the tenth wiring and the eleventh wiring and one of the twelfth wirings, the seventh terminal being electrically connected to the one of the tenth wiring and the eleventh wiring, and the eighth terminal being electrically connected to the one of the twelfth wirings; a plurality of thirteenth wirings disposed to correspond to the twelfth wirings and extending in the first direction, each of the thirteenth wirings disposed to be in contact with a face of corresponding one of the twelfth wirings opposite to the fourth resistive change elements; a fourteenth wiring and a fifteenth wiring disposed at a sixth level, extending in the third direction, and separated from each other, the fifth level being between the sixth level and the fourth level, a region between the tenth wiring and the eleventh wiring, a region between the eighth wiring and the ninth wiring, a region between the fourth wiring and the fifth wiring, and a region between the second wiring and the third wiring being located at positions in the second direction from a portion of the fourteenth wiring; a plurality of fifth resistive change elements each including a ninth terminal and a tenth terminal and disposed between one of the thirteenth wirings and one of the fourteenth wiring and the fifteenth wiring, the ninth terminal being electrically connected to the one of the thirteenth wirings, and the tenth terminal being electrically connected to the one of the fourteenth wiring and the fifteenth wiring; a sixteenth wiring disposed to be in contact with a face of the fourteenth wiring opposite to the thirteenth wirings and extending in the third direction; a seventeenth wiring disposed to be in contact with a face of the fifteenth wiring opposite to the thirteenth wirings and extending in the third direction, and separated from the sixteenth wiring; a plurality of eighteenth wirings disposed at a seventh level and extending in the first direction, the sixth level being between the seventh level and the fifth level; a plurality of sixth resistive change elements each including an eleventh terminal and a twelfth terminal and disposed between one of the sixteenth wiring and the seventeenth wiring and one of the eighteenth wirings, the eleventh terminal being electrically connected to the one of the sixteenth wiring and the seventeenth wiring, and the twelfth terminal being electrically connected to the one of the eighteenth wirings; a plurality of nineteenth wirings disposed to correspond to the eighteenth wirings and extending in the first direction, each of the nineteenth wirings disposed to be in contact with a face of corresponding one of the eighteenth wirings opposite to the sixth resistive change elements; a twentieth wiring and a twenty-first wiring disposed at an eighth level, extending in the third direction, and separated from each other, the seventh level being between the eighth level and the sixth level, a region between the sixteenth wiring and the seventeenth wiring, a region between the fourteenth wiring and the fifteenth wiring, a region between the tenth wiring and the eleventh wiring, a region between the eighth wiring and the ninth wiring, a region between the fourth wiring and the fifth wiring, and a region between the second wiring and the third wiring being located at positions in the second direction from a portion of the twentieth wiring; a plurality of seventh resistive change elements each including a thirteenth terminal and a fourteenth terminal and disposed between one of the nineteenth wirings and one of the twentieth wiring and the twenty-first wiring, the thirteenth terminal being electrically connected to the one of the nineteenth wirings, and the fourteenth terminal being electrically connected to the one of the twentieth wiring and the twenty-first wiring; a twenty-second wiring disposed to be in contact with a face of the twentieth wiring opposite to the nineteenth wirings and extending in the third direction; a twenty-third wiring disposed to be in contact with a face of the twenty-first wiring opposite to the nineteenth wirings and extending in the third direction, and separated from the twenty-second wiring; a plurality of twenty-fourth wirings disposed at a ninth level and extending in the first direction, the eighth level being between the ninth level and the seventh level; a plurality of eighth resistive change elements each including a fifteenth terminal and a sixteenth terminal and disposed between one of the twenty-second wiring and the twenty-third wiring and one of the twenty-fourth wirings, the fifteenth terminal being electrically connected to the one of the twenty-second wiring and the twenty-third wiring, and the sixteenth terminal being electrically connected to the one of the twenty-fourth wirings; a first contact electrically connected to a portion of the third wiring; a second contact electrically connected to an end of the ninth wiring on a side of the eighth wiring, and passing through the region between the fourth wiring and the fifth wiring and the region between the second wiring and the third wiring; a third contact electrically connected to an end of the fourteenth wiring on a side of the fifteenth wiring, and passing through the region between the tenth wiring and the eleventh wiring, the region between the eighth wiring and the ninth wiring, the region between the fourth wiring and the fifth wiring, and the region between the second wiring and the third wiring; and a fourth contact electrically connected to the portion of the twentieth wiring, and passing through the region between the sixteenth wiring and the seventeenth wiring, the region between the fourteenth wiring and the fifteenth wiring, the region between the tenth wiring and the eleventh wiring, the region between the eighth wiring and the ninth wiring, the region between the fourth wiring and the fifth wiring, and the region between the second wiring and the third wiring.
 7. The semiconductor memory device according to claim 6, further comprising: a first driving circuit configured to drive the third wiring through the first contact; a second driving circuit configured to drive the ninth wiring through the second contact; a third driving circuit configured to drive the fourteenth wiring through the third contact; and a fourth driving circuit configured to drive the twentieth wiring through the fourth contact.
 8. The semiconductor memory device according to claim 7, further comprising: a fifth contact electrically connected to an end of the fifteenth wiring opposite to the fourteenth wiring; a fifth driving circuit configured to drive the fifteenth wiring through the fifth contact; a sixth contact electrically connected to a portion of the twenty-first wiring; and a sixth driving circuit configured to drive the twenty-first wiring through the sixth contact.
 9. The semiconductor memory device according to claim 8, wherein a length of the fifteenth wiring in the third direction is longer than a length of each of the third wiring and the fifth wiring in the third direction.
 10. The semiconductor memory device according to claim 6, wherein at least one of the first to the eighth resistive change elements contain chalcogenide.
 11. The semiconductor memory device according to claim 6, wherein a length of the ninth wiring in the third direction is longer than a length of each of the third wiring and the fifth wiring in the third direction.
 12. A semiconductor memory device comprising: a plurality of first wirings disposed at a first level and extending in a first direction; a second wiring and a third wiring disposed at a second level, a position of which in a second direction intersecting with the first direction is different from that of the first level, the second wiring and the third wiring extending in a third direction that intersects with the first direction and the second direction, and being separated from each other; a plurality of first resistive change elements each including a first terminal and a second terminal and disposed between one of the first wirings and one of the second wiring and the third wiring, the first terminal being electrically connected to the one of the first wirings, and the second terminal being electrically connected to the one of the second wiring and the third wiring; a fourth wiring disposed to be in contact with a face of the second wiring opposite to the first wirings and extending in the third direction; a fifth wiring disposed to be in contact with a face of the third wiring opposite to the first wirings, extending in the third direction, and separated from the fourth wiring; a plurality of sixth wirings disposed at a third level and extending in the first direction, the second level being between the first level and the third level; a plurality of second resistive change elements each including a third terminal and a fourth terminal and disposed between one of the fourth wiring and the fifth wiring and one of the sixth wirings, the third terminal being electrically connected to the one of the fourth wiring and the fifth wiring, and the fourth terminal being electrically connected to the one of the sixth wirings; a plurality of seventh wirings disposed to correspond to the sixth wirings and extending in the first direction, each of the seventh wirings being disposed to be in contact with a face of corresponding one of the sixth wirings opposite to the second resistive change elements; an eighth wiring and a ninth wiring disposed at a fourth level, extending in the third direction, and separated from each other, the third level being between the fourth level and the second level; a plurality of third resistive change elements each including a fifth terminal and a six terminal and disposed between one of the seventh wirings and one of the eighth wiring and the ninth wiring, the fifth terminal being electrically connected to the one of the seventh wirings, and the six terminal being electrically connected to the one of the eighth wiring and the ninth wiring; a tenth wiring disposed to be in contact with a face of the eighth wiring opposite to the seventh wirings and extending in the third direction; an eleventh wiring disposed to be in contact with a face of the ninth wiring opposite to the seventh wirings and extending in the third direction, and separated from the tenth wiring; a plurality of twelfth wirings disposed at a fifth level and extending in the first direction, the fourth level being between the fifth level and the third level; a plurality of fourth resistive change elements each including a seventh terminal and an eighth terminal and disposed between one of the tenth wiring and the eleventh wiring and one of the twelfth wirings, the seventh terminal being electrically connected to the one of the tenth wiring and the eleventh wiring, and the eighth terminal being electrically connected to the one of the twelfth wirings; and a first contact electrically connected to a portion of the eighth wiring, and passing through a region between the fourth wiring and the fifth wiring and a region between the second wiring and the third wiring.
 13. The semiconductor memory device according to claim 12, further comprising: a second contact electrically connected to a portion of the third wiring; and a first driving circuit configured to drive the eighth wiring through the first contact; and a second driving circuit configured to drive the third wiring through the second contact.
 14. The semiconductor memory device according to claim 12, wherein at least one of the first to the fourth resistive change elements contains chalcogenide. 